1. Field of the Invention
The present invention relates generally to computer architecture, and more specifically to a processor capable of executing instructions from multiple instruction sets.
2. Background Art
It is well known that computer systems (e.g., main frames, personal computers, microprocessors, etc.) may be designed to execute instructions from more than one instruction set. In such a situation, for example, a first instruction set might be optimized for fast execution on a target system. However, instructions from this first set might have a relatively wide format (e.g., 32 or 64 bits in width) and therefore use a relatively large amount of memory space for storage. Hence, a second instruction set could be made available that is optimized for using less memory space through the use of a narrower instruction width format (e.g., 8 or 16 bits in width). Such instructions may execute routines slower than those from the first instruction set (because more and possibly different instructions are required to carry out the same function), but the narrower format contributes to a potential reduction in overall memory space required. Additionally, a third instruction set could be made available to provide backwards compatibility to earlier generation machines that, again, may utilize instruction width formats of differing size (e.g., older 16-bit machines). Moreover, a fourth (or more) instruction set could be made available to provide upwards compatibility to new developments in instruction sets that may also require different instruction width formats (e.g., 8-bit JAVA bytecodes). The foregoing examples, of course, are not exhaustive.
In order for a single computer system to support two or more instruction sets as described above, the system requires the capability to accommodate different instruction width formats. Such capability may be achieved by mapping one instruction set onto another, which thereby necessitates only a single decoder for such different formats. Such mapping is possible where the one instruction set is a subset of the other. However, this is a significantly limiting feature since most instruction sets are not so related.
Moreover, this issue is made more complex in computer systems using multi-way caches that simultaneously output a plurality of instructions to select from. Mapping may be achieved in such a system through a series of operations carried out in one or more pipeline stages (of a pipelined processor). These operations include reading a plurality of instructions from a cache memory, and processing such instructions by tag comparing each instruction, selecting a desired instruction from the plurality (based on the tag compare) and then mapping the desired instruction. However, in such a serial method, the processing of these instructions results in a branch penalty and/or increased cycle time.
Therefore, what is needed is a more efficient and flexible mechanism for mapping instructions of a plurality of instruction sets for execution on a single computer system.